Title :
A 65 nm Low-Power Adaptive-Coupling Redundant Flip-Flop
Author :
Masuda, Masahiro ; Kubota, K. ; Yamamoto, Ryo ; Furuta, J. ; Kobayashi, Kaoru ; Onodera, Hidetoshi
Author_Institution :
Grad. Sch. of Sci. & Technol., Kyoto Inst. of Technol., Kyoto, Japan
Abstract :
We propose a low-power redundant flip-flop to be operated with high reliability over 1 GHz clock frequency based on the low-power (ACFF) and the highly-reliable (BCDMR) flip-flops. Its power dissipation is almost equivalent to the transmission-gate FF at 10% data activity while paying 3 × area penalty. Experiments by α-particle and neutron irradiation reveal its highly-reliable operations with no error at 1.2 V and 1 GHz. We measured five different process corner chips by α irradiation. Soft error rates are almost equivalent in these corner chips.
Keywords :
alpha-particle effects; clocks; flip-flops; integrated circuit reliability; low-power electronics; neutron effects; radiation hardening (electronics); α-particle irradiation; BCDMR flip-flops; adaptive-coupling flip-flop; clock frequency; frequency 1 GHz; low-power redundant flip-flop; neutron irradiation; power dissipation; reliability; size 65 nm; soft error rates; voltage 1.2 V; Clocks; Latches; Neutrons; Power dissipation; Radiation effects; Reliability; Semiconductor device measurement; flip-flop; 65 nm bulk CMOS; adaptive-coupled flip-flop (ACFF); bi-stable cross-coupled dual modular redundancy (BCDMR); built-in soft-error resilience (BISER); low-power; multiple cell upset (MCU); radiation-hard design;
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.2013.2245344
