A Flexible Hardware Architecture for Wavelet Packet Transform With Arbitrary Tree Structure

Author

Garcia, D. ; Mansour, Moussa ; Ali, Mohamed

Author_Institution

Syst. & Applic. R&D Center, Texas Instrum. Inc., Dallas, TX, USA

Volume

60

Issue

10

fYear

2013

fDate

Oct. 2013

Firstpage

657

Lastpage

661

Abstract

We present a new hardware architecture for implementing the orthogonal wavelet packet transform with an arbitrary wavelet tree. The architecture is flexible enough to accommodate an arbitrary wavelet filter and an arbitrary tree up to a certain depth. The tree structure is specified through an efficient register parameterization architecture. We provide a detailed description of the different modules and complexity estimates for the application-specified integrated circuit implementation of the proposed architecture.

Keywords

application specific integrated circuits; compressed sensing; filtering theory; trees (mathematics); wavelet transforms; application specified integrated circuit; arbitrary tree structure; arbitrary wavelet filter; arbitrary wavelet tree; efficient register parameterization architecture; flexible hardware architecture; orthogonal wavelet packet transform; Complexity theory; Computer architecture; Multiplexing; Registers; Wavelet packets; Application-specified integrated circuit (ASIC); sensor compression; wavelet packets; wavelet tree;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2013.2277964

Filename

6587498