DocumentCode :
1765186
Title :
Interface Engineering of Ag- {\\rm GeS}_{2} -Based Conductive Bridge RAM for Reconfigurable Logic Applications
Author :
Palma, G. ; Vianello, E. ; Thomas, O. ; Suri, Manan ; Onkaraiah, S. ; Toffoli, A. ; Carabasse, C. ; Bernard, M. ; Roule, A. ; Pirrotta, O. ; Molas, G. ; De Salvo, B.
Author_Institution :
Adv. Memory Technol. Lab., CEA, Grenoble, France
Volume :
61
Issue :
3
fYear :
2014
fDate :
41699
Firstpage :
793
Lastpage :
800
Abstract :
In this paper, we show performance and reliability improvement of Ag- GeS2-based conductive bridge RAM (CBRAM) devices by addition of a 2-nm-thick HfO2 layer between the electrolyte and the W bottom electrode. Our optimized dual-layer electrolyte stack (2-nm HfO2-30-nm GeS2) leads to a resistance ratio (ROFF/RON) higher than 106 and projected 10 years read disturb immunity at 0.04 V. The improved memory resistance ratio is explained by means of physical modeling. Using compact modeling and circuit level simulations, we show that our optimized CBRAM device, integrated in a 1T-2R architecture, fits well with the aggressive requirements of field programmable gate array-type reconfigurable applications. Nonvolatility, back-end-of-line compatibility, and 1.3-nA leakage current during continuous reverse read operation at 1 V are strong benefits demonstrated on our device for such applications.
Keywords :
electrolytes; field programmable gate arrays; germanium compounds; hafnium compounds; random-access storage; silver; 1T-2R architecture; Ag-GeS2; CBRAM devices; HfO2; bottom electrode; circuit level simulations; compact modeling; conductive bridge RAM devices; continuous reverse read operation; current 1.3 nA; electrolyte; field programmable gate array-type reconfigurable applications; interface engineering; leakage current; memory resistance ratio; nonvolatility back-end-of-line compatibility; optimized dual-layer electrolyte stack; physical modeling; read disturb immunity; reconfigurable logic applications; reliability improvement; size 2 nm; size 30 nm; voltage 0.04 V; voltage 1 V; Computer architecture; Hafnium compounds; Logic gates; Random access memory; Resistance; Switches; Voltage measurement; Conductive bridge RAM (CBRAM); disturb immunity; field-programmable gate array (FPGA); resistance ratio;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2014.2301694
Filename :
6740008
Link To Document :
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