Title :
Impact of Using Double-Patterning Versus Single-Patterning on Threshold Voltage
Variation in Quasi-Planar Tri-Gate Bulk MOSFETs
Author :
Changhwan Shin ; In Jun Park
Author_Institution :
Univ. of Seoul, Seoul, South Korea
Abstract :
To experimentally investigate the impact of double-patterning and double-etching (2P2E) versus single-patterning and single-etching (1P1E) on the line-edge-roughness (LER) as well as on the LER-induced threshold-voltage (VTH) variation in a multigate bulk device, quasi-planar tri-gate (QPT) bulk metal-oxide semiconductor field-effect transistors (MOSFETs) are fabricated by a 28-nm complementary metal-oxide-semiconductor (CMOS) technology. It is experimentally verified that the LER profile obtained through using the 2P2E 193-nm immersion photolithography technique has a relatively longer correlation length (i.e., lower spatial frequency) than that by the 1P1E technique, although they have a comparable root-mean-square deviation and fractal dimension. By using Monte Carlo simulations to analyze the random VTH variations in the QPT bulk MOSFETs, we confirm that the 2P2E-LER-induced VTH variation (versus the 1P1E-LER-induced VTH variation) is suppressed by ~20% in terms of σ(VTH). However, the total VTH variation in the QPT MOSFETs is slightly improved with the 2P2E technique, because the other variation sources such as random dopant fluctuation and work-function variation have still dominated the total VTH variation. To fully benefit from the 2P2E technique, the other random/intrinsic variations should be better controlled in the QPT CMOS technology.
Keywords :
CMOS integrated circuits; MOSFET; Monte Carlo methods; etching; immersion lithography; nanopatterning; work function; 1P1E; 2P2E; CMOS technology; LER-induced threshold-voltage variation; Monte Carlo simulations; QPT bulk MOSFET; complementary metal-oxide-semiconductor technology; double-etching; double-patterning; immersion photolithography; line-edge-roughness; metal-oxide semiconductor field-effect transistors; quasiplanar tri-gate bulk MOSFET; random dopant fluctuation; random-intrinsic variations; single-etching; single-patterning; size 28 nm; wavelength 193 nm; work-function variation; CMOS integrated circuits; CMOS technology; Correlation; Logic gates; MOSFET; Resource description framework; Characterization; complementary metal-oxide-semiconductor (CMOS); metal-oxide-semiconductor field-effect transistors (MOSFETs); variability;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2013.2249653