Title :
Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems
Author :
Bispo, Joao ; Paulino, Nuno ; Cardoso, Joao M. P. ; Ferreira, J.C.
Author_Institution :
INESC-ID, Lisboa, Portugal
Abstract :
This paper presents a novel approach to accelerate program execution by mapping repetitive traces of executed instructions, called Megablocks, to a runtime reconfigurable array of functional units. An offline tool suite extracts Megablocks from microprocessor instruction traces and generates a Reconfigurable Processing Unit (RPU) tailored for the execution of those Megablocks. The system is able to transparently movebcomputations from the microprocessor to the RPU at runtime. A prototype implementation of the system using a cacheless MicroBlaze microprocessor running code located in external memory reaches speedups from 2.2× to 18.2 × for a set of 14 benchmark kernels. For a system setup which maximizes microprocessor performance by having the application code located in internal block RAMs, speedups from 1.4 × to 2.8 × were estimated.
Keywords :
hardware-software codesign; microprocessor chips; random-access storage; reconfigurable architectures; Megablocks; RPU; benchmark kernels; cacheless MicroBlaze microprocessor running code; executed instruction mapping; external memory; functional runtime reconfigurable array units; internal block RAM; microprocessor instruction traces; microprocessor performance maximization; offline tool suite; program execution; reconfigurable HW/SW systems; reconfigurable processing unit; transparent trace-based binary acceleration; Acceleration; Arrays; Central Processing Unit; Hardware; Pattern matching; Runtime; Binary translation; hardware accelerator; instruction traces; megablock; reconfigurable computing;
Journal_Title :
Industrial Informatics, IEEE Transactions on
DOI :
10.1109/TII.2012.2235844