• DocumentCode
    1765446
  • Title

    Failure mechanism for input buffer under CDM test

  • Author

    Tzu-Cheng Kao ; Chung-Yu Hung ; Jian-Hsing Lee ; Chen-Hsin Lien ; Chien-Wei Chiu ; Kuo-Hsuan Lo ; Hung-Der Su ; Wu-Te Weng

  • Author_Institution
    Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
  • Volume
    50
  • Issue
    9
  • fYear
    2014
  • fDate
    April 24 2014
  • Firstpage
    667
  • Lastpage
    669
  • Abstract
    The influence of the body layout on the charged device model (CDM) failure site and the robustness of the input buffer is explored. The failure analysis results confirm that the gate oxide is damaged. The failure site can be moved from the region above the channel to the overlap region between the source and the gate once the body layout is cut from a ring into a small segment, providing direct evidence demonstrating that the CDM current flows through the gate oxide via the body and the source of the transistor, since both connect to the Vss bus line. Otherwise, changing the body layout of the input buffer transistor does not vary the failure location.
  • Keywords
    buffer circuits; electric charge; failure analysis; integrated circuit reliability; integrated circuit testing; semiconductor device reliability; transistors; CDM current flow; CDM testing; Vss bus line; body layout influence; charged device model; failure mechanism analysis; gate oxide; input buffer transistor;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el.2013.4094
  • Filename
    6809285