DocumentCode :
1765753
Title :
Improved High Code-Rate Soft BCH Decoder Architectures With One Extra Error Compensation
Author :
Yi-Min Lin ; Hsie-Chia Chang ; Chen-Yi Lee
Author_Institution :
Electr. Eng. Dept., Univ. of California, Los Angeles, Los Angeles, CA, USA
Volume :
21
Issue :
11
fYear :
2013
fDate :
Nov. 2013
Firstpage :
2160
Lastpage :
2164
Abstract :
Compared with traditonal hard Bose-Chaudhuri-Hochquenghem (BCH) decoders, soft BCH decoders provide better error-correcting performance but much higher hardware complexity. In this brief, an improved soft BCH decoding algorithm is presented to achieve both competitive hardware complexity and better error-correcting performance by dealing with least reliable bits and compensating one extra error outside the least reliable set. For BCH (255, 239; 2) and (255, 231; 3) codes, our proposed soft BCH decoders can achieve up to 0.75-dB coding gain with one extra error compensation and 5% less complexity than the traditional hard BCH decoders.
Keywords :
decoding; error compensation; error correction codes; Bose-Chaudhuri-Hochquenghem; error-correcting performance; hardware complexity; improved high code-rate soft BCH decoder architecture; one extra error compensation; Complexity theory; Decoding; Hardware; Multiplexing; Registers; Reliability; Vectors; Bose-Chaudhuri-Hochquenghem (BCH) codes; error-correction coding; soft decoding;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2012.2227847
Filename :
6392304
Link To Document :
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