Correlation Between TLP, HMM, and System-Level ESD Pulses for Cu Metallization

Correlation factors between different ESD pulse types for different back-end-of-line (BEOL) metal-line topologies have been studied to support system-level on-chip ESD design. The component level (HMM, HBM, and TLP on a wafer) and system-level (IEC gun contact on package) ESD stresses were correlated followed by extraction of correlation factors between the IEC/HMM and TLP, as well as the HBM and TLP supported by analytical approximation. The major conclusions were verified using the thermal coupled mixed-mode simulation analysis.