A Silicon Biristor With Reduced Operating Voltage: Proposal and Analysis

Author

Kumar, Mamidala Jagadesh ; Maheedhar, M. ; Varma, P.P.

Author_Institution

Dept. of Electr. Eng., Indian Inst. of Technol. Delhi, New Delhi, India

Volume

3

Issue

2

fYear

2015

fDate

42064

Firstpage

67

Lastpage

72

Abstract

In this paper, using 2-D simulations, we report a silicon biristor with reduced operating voltage using the surface accumulation layer transistor (SALTran) concept. The electrical characteristics of the proposed SALTran biristor are simulated and compared with that of a conventional silicon biristor with identical dimensions. The proposed device is optimized with respect to the device parameters to ensure a reasonable latch window while maintaining low latch voltages. Our results demonstrate that the SALTran biristor exhibits a latch-up voltage of 2.14 V and a latch-down voltage of 1.68 V leading to a 57% lower operating voltage compared to the conventional silicon biristor.

Keywords

bipolar transistors; resistors; silicon; 2-D simulation; SALTran biristor; bipolar junction transistor; bistable resistor; electrical characteristic; latch window; latch-down voltage; latch-up voltage; reduced operating voltage; silicon biristor; surface accumulation layer transistor; voltage 1.68 V; voltage 2.14 V; Bipolar transistors; Doping; Impact ionization; Latches; Semiconductor process modeling; Silicon; Transistors; Biristor; SALTran effect; bistable resistor; current gain; device optimization; open-base breakdown; surface accumulation layer transistor (SALTran) effect;

fLanguage

English

Journal_Title

Electron Devices Society, IEEE Journal of the

Publisher

ieee

ISSN

2168-6734

Type

jour

DOI

10.1109/JEDS.2014.2384518

Filename

6994257