A fully integrated CMOS linear power amplifier using an IMD-reduced bias network

Author

Sungho Lee ; Kihyun Kim ; Daeyeon Kim

Author_Institution

Convergence SoC Res. Center, Korea Electron. Technol. Inst. (KETI), Seongnam, South Korea

fYear

2014

fDate

6-9 Oct. 2014

Firstpage

1261

Lastpage

1264

Abstract

A fully integrated CMOS linear RF power amplifier (PA) that includes integrated on-chip input and output matching networks is presented. This PA consists of two-stage configuration, each of which adopts a differential cascode structure. A new gate bias network of the common source amplifier is proposed to suppress intermodulation distortion. The results of the simulation and the measurements of the proposed bias circuit are compared and verified. The PA prototype is fabricated in Dongbu 0.11-μm 1-poly 8-metal CMOS process. The measured results were 29.4 dBm of P-1dB, 34 dB of power gain, a maximum PAE of 40% for a sinusoidal signal, and a peak PAE of 34% for a 900 MHz WCDMA-modulated signal.

Keywords

CMOS integrated circuits; UHF power amplifiers; interference suppression; intermodulation distortion; Dongbu 0.11-μm 1-poly 8-metal CMOS process; IMD-reduced bias network; common source amplifier; differential cascode structure; efficiency 34 percent; efficiency 40 percent; frequency 900 MHz; fully integrated CMOS linear RF power amplifier; gain 34 dB; gate bias network; integrated on-chip input; intermodulation distortion; output matching networks; size 0.11 mum; two-stage configuration; CMOS integrated circuits; Impedance; Inductors; Linearity; Logic gates; Multiaccess communication; Power amplifiers; CMOS; IMD; Linearity; PAE; Power amplifier; RF; WCDMA;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Conference (EuMC), 2014 44th European

Conference_Location

Rome

Type

conf

DOI

10.1109/EuMC.2014.6986672

Filename

6986672