Fully integrated CMOS Doherty Power Amplifier with network matching optimization for die size reduction

Author

Carneiro, Marcos L. ; Deltimple, Nathalie ; Carvalho, Paulo H. P. ; Belot, Didier ; Kerherve, Eric

Author_Institution

Electr. Eng. Dept., Univ. of Brasilia, Brasilia, Brazil

fYear

2014

fDate

6-9 Oct. 2014

Firstpage

1269

Lastpage

1272

Abstract

Impedance network topology optimization method is proposed for saving die area and increasing performance. The technique was applied on a fully integrated Doherty Power Amplifier design in 65nm CMOS technology. Measurement results achieve a constant 24% PAE performance over a 7 dB backoff, P_out of 23.4dBm and 15dB of gain. The optimization allowed the reduction of the number of inductors which reduced in 59% the expected die area and also increased the PAE mean performance in 5% on the high power stage and the P_out in 2dB.

Keywords

CMOS integrated circuits; circuit optimisation; impedance matching; inductors; network topology; power amplifiers; PAE mean performance; die area; die size reduction; efficiency 24 percent; fully integrated CMOS Doherty power amplifier design; gain 15 dB; high power stage; impedance network topology optimization; inductors; network matching optimization; size 65 nm; CMOS integrated circuits; CMOS technology; Capacitors; Frequency measurement; Inductors; Optimization; Power amplifiers; CMOS integrated circuit; circuit optimization; design methodology; power amplifier;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Conference (EuMC), 2014 44th European

Conference_Location

Rome

Type

conf

DOI

10.1109/EuMC.2014.6986674

Filename

6986674