A 0.1pJ Freeze Vernier time-to-digital converter in 65nm CMOS

Author

Blutman, Kristof ; Angevare, Jan ; Zjajo, Amir ; van der Meijs, Nick

Author_Institution

Delft Univ. of Technol., Delft, Netherlands

fYear

2014

fDate

1-5 June 2014

Firstpage

85

Lastpage

88

Abstract

A Freeze Vernier delay line time-to-digital converter for very low power and high resolution is presented. The Freeze Vernier Delay Line is a Vernier-type TDC, where the state of the start line can be frozen by the stop line, omitting the power-hungry time capture elements like D-registers or arbiters that are usually employed in a Vernier TDC. The two main issues of the design, the charge kickback between the delay lines and the imperfect freezing are solved with additional circuitry. The TDC core consists of inverters and current-enabled inverters only. A proof-of-concept design has been implemented in 65nm CMOS with a typical resolution of 4.88ps, a dynamic energy consumption of 106.22fJ per conversion and a combined gate width of 96μm.

Keywords

CMOS integrated circuits; convertors; delay lines; integrated circuit design; invertors; CMOS; D-registers; Freeze Vernier delay line time-to-digital converter; current-enabled inverters; delay lines; dynamic energy consumption; energy 0.1 pJ; energy 106.22 pJ; power-hungry time capture elements; proof-of-concept design; size 65 nm; size 96 mum; time 4.88 ps; CMOS integrated circuits; Delay lines; Delays; Inverters; Logic gates; Ring oscillators; Signal resolution;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2014 IEEE International Symposium on

Conference_Location

Melbourne VIC

Print_ISBN

978-1-4799-3431-7

Type

conf

DOI

10.1109/ISCAS.2014.6865071

Filename

6865071