A subsampling stochastic coarse-fine ADC with SNR 55.3dB and >5.8TS/s effective sample rate for an on-chip signal analyzer

Author

Tandon, James S. ; Yamaguchi, Takahiro J. ; Komatsu, Satoshi ; Asada, Kunihiro

Author_Institution

VDEC-D2T, Univ. of Tokyo, Tokyo, Japan

fYear

2014

fDate

1-5 June 2014

Firstpage

93

Lastpage

96

Abstract

This paper presents a subsampling two-step coarse-fine stochastic A/D converter for on-chip measurement of high speed signals. Using equivalent time sampling techniques, we achieve an effective sampling rate of over 230 GS/s measurements for a 23.0023 MHz sine wave, and over 5.8 TS/s for an on-chip 2921.0115 MHz 7-bit PRBS while using a clock rate of 23 MHz. Our ADC achieves an SNR of 55.3 dB and SNDR of 40.6 dB without calibration for the sine wave measurement. We improve on previous work by reducing the number of comparators required per stochastic group while extending dynamic range to cover a rail-to-rail input signal.

Keywords

analogue-digital conversion; comparators (circuits); analog-to-digital converters; equivalent time sampling; frequency 23 MHz; frequency 23.0023 MHz; frequency 2921.0115 MHz; on-chip measurement; on-chip signal analyzer; pseudorandom binary sequence; sine wave measurement; stochastic comparator group; subsampling stochastic coarse-fine ADC; Clocks; Dynamic range; Gaussian distribution; Standards; Stochastic processes; System-on-chip; Transfer functions; ADC; analog-to-digital converter; comparator; comparator group; offset voltage; stochastic; variation;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2014 IEEE International Symposium on

Conference_Location

Melbourne VIC

Print_ISBN

978-1-4799-3431-7

Type

conf

DOI

10.1109/ISCAS.2014.6865073

Filename

6865073