A sub-ranging 2-Step 7-bit self-calibrated comparator-based binary-search ADC

The comparator-based asynchronous binary-search (CABS) analog-to-digital converter (ADC) topology is a good solution to achieve high conversion rate at low power dissipation. In this paper we present an architecture of CABS ADC with a background calibration scheme, that allows the use of smaller devices, further reducing the power consumption. Unlike the foreground calibration, it does not require the ADC precalibration before it starts to operate, reducing the system-level complexity. The calibration is performed through the use of a digital-to-analog converter (DAC) serving as reference for the self-calibrated comparators. We also propose threshold reconfigurable comparators, reducing the number of the devices used. In this paper, we design a 7-bit 2-step ADC comprehending a 2-bit successive approximation register (SAR) ADC for the front-end and the proposed 5-bit CABS ADC for the back-end. Monte-Carlo simulations for the 2-step design show that, sampling at 250MSps, the ADC has 450μW of power consumption with a 6.92 effective number of bits resulting in a figure of merit of 14.86fJ/conversion step.