Multiple-clock multiple-edge-triggered multiple-bit flip-flops for two-phase handshaking asynchronous circuits

This paper proposes multiple-clock multiple-edge-triggered multiple-bit flip-flops for designing simple and straight-forward asynchronous control circuits of the two-phase handshaking protocol. The proposed flip-flops have multiple clocks and multiple data inputs, and each data input can be stored in the flip-flop at both the rising edge and the falling edge of the corresponding clock. They can be applied in the asynchronous design of the two-phase handshaking protocol not only for synthesizing simple control circuits, but also for obtaining robust circuits. The performance of the proposed flip-flops have been evaluated using the PTM 22 nm HP device parameters.