A 2 GOPS quad-mean shift processor with early termination for machine learning applications

Author

Chang-Hung Tsai ; Hui-Hsuan Lee ; Wan-Ju Yu ; Chen-Yi Lee

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2014

fDate

1-5 June 2014

Firstpage

157

Lastpage

160

Abstract

This paper proposes a 2 GOPS quad-mean shift processor (Q-MSP) architecture for data clustering and machine learning applications. By exploiting the linear approximation approach and early termination mechanism, the proposed algorithm can reduce 70% and 40% computational complexity, respectively. Moreover, 4 mean shift processor cores are integrated into the proposed architecture to support parallel processing to further improve system performance. Implemented in Xilinx Virtex-7 FPGA, this architecture occupies 65k LUTs and 3.3MB block memory to achieve 2 GOPS throughput operated at 125MHz.

Keywords

computational complexity; data mining; learning (artificial intelligence); multiprocessing systems; parallel processing; pattern clustering; 2 GOPS quad-mean shift processor architecture; Q-MSP; Xilinx Virtex-7 FPGA; block memory; computational complexity; data clustering; early termination mechanism; linear approximation approach; machine learning applications; mean shift processor cores; parallel processing; Algorithm design and analysis; Approximation algorithms; Computer architecture; Engines; Linear approximation; Parallel processing; Training data;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2014 IEEE International Symposium on

Conference_Location

Melbourne VIC

Print_ISBN

978-1-4799-3431-7

Type

conf

DOI

10.1109/ISCAS.2014.6865089

Filename

6865089