Architectures for polar BP decoders using folding

Capacity-achieving polar codes have received significant attention in past few years. These codes can be decoded using either the successive-cancellation (SC) approach or the belief propagation (BP) approach. Several VLSI architectures of SC polar decoders have been reported in the literature. However, SC decoders suffer from long latency and low throughput due to their sequential decoding nature. On the other hand, although the BP decoders can be operated in an inherently parallel manner with high throughput, the functional units in these decoders are underutilized. In this paper, we exploit various architecture transformation techniques to further improve hardware performance of polar BP decoders. First, we propose an overlapped-scheduling approach at iteration level to reduce the overall decoding latency. Second, we propose codeword-level overlap to further improve hardware utilization efficiency. Third, we show that the above two overlapping approaches can be unified into a general framework into a joint overlapping approach. Fourth, we exploit the folding technique to design low-complexity polar BP decoders, and present two types of folded architectures. Synthesis results show that the proposed two (1024, 512) polar BP decoder designs can achieve 1.50 and 2.43 times reduction in hardware complexity, respectively. In addition, the proposed two designs can also achieve 7.4 and 2.5 times improvement in hardware efficiency, respectively.