DocumentCode :
1768432
Title :
A 28nm programmable and low power ultra-HD video codec engine
Author :
Sanghvi, Hetul ; Mody, Mihir ; Nandan, Nibedita ; Mehendale, Mahesh ; Das, S. ; Mandal, Dipan Kumar ; Shastry, Pavan
Author_Institution :
Texas Instrum. Inc., Bangalore, India
fYear :
2014
fDate :
1-5 June 2014
Firstpage :
558
Lastpage :
561
Abstract :
Video codec standards like H.264 and HEVC are driving the need for high computation and high memory bandwidth in current SOCs. On the other hand, portable devices like smartphones and tablets are driving the need to reduce power consumption for enhanced battery life. In this paper, we present a scalable H.264 Ultra-HD video codec engine that dissipates 9 mW of decode and 18 mW of encode power (for a typical HP H.264 1080p30 bit-stream) in 28 nm low power process technology node using various low power optimization techniques across architecture, design, circuit, software and systems.
Keywords :
video codecs; video coding; HEVC; SOC; low power optimization techniques; low power process technology node; low power ultra-HD video codec engine; scalable H.264 Ultra-HD video codec engine; Bandwidth; Clocks; Engines; Optimization; SDRAM; Streaming media; Video codecs; 4K; AVC; Architecture; H.264; HEVC; Low Power; Multi-format; Ultra HDTV; VLSI; Video Engine;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2014 IEEE International Symposium on
Conference_Location :
Melbourne VIC
Print_ISBN :
978-1-4799-3431-7
Type :
conf
DOI :
10.1109/ISCAS.2014.6865196
Filename :
6865196
Link To Document :
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