• DocumentCode
    1768452
  • Title

    A new fault injection method for evaluation of combining SEU and SET effects on circuit reliability

  • Author

    Kejun Wu ; Pahlevanzadeh, Hoda ; Peng Liu ; Qiaoyan Yu

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of New Hampshire, Durham, NH, USA
  • fYear
    2014
  • fDate
    1-5 June 2014
  • Firstpage
    602
  • Lastpage
    605
  • Abstract
    We propose a new dual-level fault injection method for evaluating combination effect of single event upsets (SEUs) and single event transients (SETs). The proposed interaction method allows collaborative simulation on register-transfer level (RTL) and gate level. Conventional fault injection methods or fault model techniques typically aim at SEUs or SETs, rather than the combination of SETs and SEUs. As a logic depth and clock period decrease, SEUs and SET are likely to co-exist, which further challenges circuit reliability. To facilitate the investigation of advanced SEU and SET management methods, our fault injection method considers both SETs and SEUs. We apply the proposed method to two ITC´99 benchmark circuits to analyze the mutual masking effect between SETs and SEUs. Simulations performed on the two circuits show that SET duration time is the dominant factor affecting the mutual masking effect. If SEU duration time changes (but not beyond one cycle), the maximum masked error ratio is up to five times the minimum masked error ratio. We also observed that doubling clock frequency results in the average masked error ratio varying from 3% to 10%.
  • Keywords
    integrated circuit reliability; integrated circuit testing; logic circuits; radiation hardening (electronics); ITC´99 benchmark circuits; RTL; SET duration time; SET effects; SET management methods; SEU duration time; SEU effects; SEU management methods; circuit reliability; clock frequency; clock period; dual-level fault injection method; fault model techniques; gate level; interaction method; logic depth; masked error ratio; mutual masking effect; register-transfer level; single event transients; single event upsets; Circuit faults; Clocks; Integrated circuit modeling; Integrated circuit reliability; Logic gates; Single event upsets; ITC´99; SET; SEU; combining effect; error masking; fault injection; reliability;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (ISCAS), 2014 IEEE International Symposium on
  • Conference_Location
    Melbourne VIC
  • Print_ISBN
    978-1-4799-3431-7
  • Type

    conf

  • DOI
    10.1109/ISCAS.2014.6865207
  • Filename
    6865207