DocumentCode
1768513
Title
A 6th order, 700–1100 MHz, 3.6 Gb/s RF bandpass ΣΔ ADC with two-tone SFDR 67.2 dB in 65nm CMOS
Author
Liang Zou ; Karthaus, Udo ; Sukumaran, Deepti ; Mehrtash, Nasser ; Wagner, Hannes
Author_Institution
ULM, Ubidyne GmbH, Germany
fYear
2014
fDate
1-5 June 2014
Firstpage
714
Lastpage
717
Abstract
This paper presents a 6th order, 700-1100 MHz, 3.6-Gb/s sampling continuous-time band-pass sigma-delta (CT BP ΣΔ) ADC realized in 65 nm CMOS technology. A high linearity transconductance-stage with Miller effect cancellation is proposed to provide above 30 dBm IIP3 over PVT corners. A 4-bit quantizer and non-return to zero (NRZ) feedback DACs are engaged in this design. The post-layout simulation shows a maximum 67.2 dB two-tone SFDR in 1-MHz bandwidth, IIP3 and noise figure are 4.3 dBm and 17.3 dB, respectively.
Keywords
CMOS digital integrated circuits; band-pass filters; continuous time filters; sigma-delta modulation; CMOS technology; Miller effect cancellation; PVT corners; RF bandpass ΣΔ ADC; bandwidth 1 MHz; bit rate 3.6 Gbit/s; continuous-time band-pass sigma-delta ADC; frequency 700 MHz to 1100 MHz; high linearity transconductance-stage; noise figure 17.3 dB; non-return to zero feedback DAC; post-layout simulation; quantizer; size 65 nm; word length 4 bit; Bandwidth; CMOS integrated circuits; Radio frequency; Receivers; Signal to noise ratio; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), 2014 IEEE International Symposium on
Conference_Location
Melbourne VIC
Print_ISBN
978-1-4799-3431-7
Type
conf
DOI
10.1109/ISCAS.2014.6865235
Filename
6865235
Link To Document