Fast parallel CRC implementation in software

A cyclic redundancy check (CRC) is one of the most commonly used error detecting codes in communication and storage devices. Before a message is transferred, a transmitter calculates the CRC using the agreed upon polynomial called a generator, and attaches the resulting residue to the message. When the message is received, a receiver calculates the CRC using the same polynomial and verifies the message. If the two CRC values are different, it means an error has occurred during the data transfer. A CRC is easy to implement in hardware using linear feedback shift registers or in software using a simple polynomial evaluation, or a table lookup for a faster speed. In this paper, a fast CRC computation is presented using a software based parallelization scheme. In an ARM Cortex-A15 implementation of the proposed methodology, it achieves 2.6 times faster speed compared to a conventional table lookup CRC computation.