A high-speed PRBS generator using flip-flops employing feedback for distributed equalization

This paper presents an inductorless full rate pseudo-random binary sequence generator (PRBSG). Data rate of the PRBSG can be enhanced by 23% using internal pre-emphasis. The technique uses D flip-flops (DFFs) as 1-tap decision feedback equalizers (DFE) to equalize the outputs of the previous DFFs. This makes every DFF a DFE circuit, which is also used as a delay element for the PRBSG. The proposed technique increases the data-rate of the PRBSG significantly with minor increase in area and power. A design methodology to find the feedback factor of pre-emphasis technique using least square estimation is also presented. Post layout simulation in standard 90 nm CMOS technology of the 2⁷-1 PRBSG confirms operation of the circuit at a data-rate of 13 Gb/s with peak to peak jitter of 8 ps, while consuming 222 mW off a 1 V supply, without using inductors.