Optimal techniques for assigning inter-tier signals to 3D-vias with path control in a 3DIC

3-dimensional integrated circuit (3DIC) technology is one of the most promising solution to meet the ever-increasing demands for higher device integration and energy-efficiency, while remaining cost-effective, for the current semiconductor industry. In a 3DIC, signals between the tiers are interconnected using top metal layer bondpoints (micro-bumps) or through-silicon-vias (TSVs). These vertical connections are called 3Dvias. Similar to I/O signals, inter-tier signals assigned to 3Dvias influence the standard cell placement in a tier, making this assignment critical for an efficient 3DIC layout. Unlike I/O signals, these inter-tier signals are very large in number and manual assignment (like assigning I/O signals to pins) is impractical and calls for automated techniques. This paper introduces several techniques that provide an optimum assignment and path control with an ability to control critical path lengths for interconnecting inter-tier signals. Ten 3DICs of two designs (5 each) are built using the proposed techniques and an architecture-driving manual assignment. The proposed techniques successfully automate the assignment process, and results show that they achieve up to 9.4% lower total wire length and 10.4% shorter average net length compared to a manual method, and up to 12% lower total and average net length compared to prior work.