Title :
An LSI implementation of a bit-parallel cellular multiplier over GF(24) using secure charge-sharing symmetric adiabatic logic
Author :
Monteiro, Carlos ; Takahashi, Y. ; Sekine, Taku
Author_Institution :
Grad. Sch. of Eng., Gifu Univ., Gifu, Japan
Abstract :
This paper presents a measurement result of a bit-parallel multiplier over GF(24) using a secure dual-rail charge-sharing symmetric adiabatic logic. The output functionality and the supply current traces of the fabricated LSI chip are measured in order to analyze the correlation of the current-to-data dependency in respect to the given input signal transitions for resistance against power analysis attack. Furthermore, the verification of the output signals of the LSI chip is measured at dynamic power clock frequency from 0.5-5 MHz.
Keywords :
integrated circuit manufacture; large scale integration; logic circuits; multiplying circuits; LSI; bit-parallel cellular multiplier; charge-sharing symmetric adiabatic logic; frequency 0.5 MHz to 5 MHz; large scale integration; power analysis attack; power clock frequency; CMOS integrated circuits; Cryptography; Current measurement; Frequency measurement; Large scale integration; Power measurement; Semiconductor device measurement;
Conference_Titel :
Circuits and Systems (ISCAS), 2014 IEEE International Symposium on
Conference_Location :
Melbourne VIC
Print_ISBN :
978-1-4799-3431-7
DOI :
10.1109/ISCAS.2014.6865263
