An LSI implementation of a bit-parallel cellular multiplier over GF(24) using secure charge-sharing symmetric adiabatic logic

This paper presents a measurement result of a bit-parallel multiplier over GF(2⁴) using a secure dual-rail charge-sharing symmetric adiabatic logic. The output functionality and the supply current traces of the fabricated LSI chip are measured in order to analyze the correlation of the current-to-data dependency in respect to the given input signal transitions for resistance against power analysis attack. Furthermore, the verification of the output signals of the LSI chip is measured at dynamic power clock frequency from 0.5-5 MHz.