A continuous-time ΔΣ modulator with a digital technique for excess loop delay compensation

A 3^rd-order continuous-time ΔΣ modulator with a highly-digital technique for excess loop delay (ELD) compensation is reported. A digitally controlled reference switching matrix is used to replace the commonly used power-hungry signal adder and extra DAC driving the quantizer. The feedback DAC is embedded in the quantizer, and implemented by a few switches. The proposed technique helps the modulator tolerate excess loop delay up to half a clock period. The modulator achieves an SQNR of 83.3 dB in a 15 MHz signal bandwidth. The use of a 2-bit FIR feedback DAC lowers the jitter-induced noise by about 10 dB. The simulated power consumption of the modulator is 7 mW.