• DocumentCode
    1768673
  • Title

    Decoupling network optimization in high speed systems by mixed-integer programming

  • Author

    Tripathi, J.N. ; Mahajan, Aditya ; Mukherjee, Jayanta ; Nagpal, R.K. ; Malik, Rohit ; Gupta, Neeraj

  • Author_Institution
    Dept. of Electr. Eng., IIT Bombay, Mumbai, India
  • fYear
    2014
  • fDate
    1-5 June 2014
  • Firstpage
    1010
  • Lastpage
    1013
  • Abstract
    Power Integrity is maintained in a high speed system by designing an efficient decoupling network. This paper provides a generic formulation for decoupling capacitor selection and placement problem which is solved by mixed-integer programming. A real-world example is presented for the same. The minimum number of capacitors that could achieve the target impedance over the desired frequency range are found along with their optimal locations. In order to solve an industrial problem, the s-parameters data of power plane geometry and capacitors are used for the accurate analysis including bulk capacitors and VRM.
  • Keywords
    S-parameters; capacitors; circuit optimisation; high-speed integrated circuits; integer programming; power supply circuits; VRM; bulk capacitors; decoupling capacitor selection; decoupling network optimization; generic formulation; high speed systems; industrial problem; mixed-integer programming; placement problem; power integrity; power plane geometry; s-parameters data; Capacitors; Decoupling Capacitors; Mixed-Integer Programming; Power Delivery Networks; Power Integrity; S-parameters;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (ISCAS), 2014 IEEE International Symposium on
  • Conference_Location
    Melbourne VIC
  • Print_ISBN
    978-1-4799-3431-7
  • Type

    conf

  • DOI
    10.1109/ISCAS.2014.6865309
  • Filename
    6865309