Efficient VLSI architectures for matrix inversion in soft-input soft-output MMSE MIMO detectors

A computational complexity analysis of matrix inversion used in soft-input soft-output minimum mean square error (MMSE) MIMO detectors and a comprehensive literature comparison of corresponding VLSI implementations are presented. They indicate that the application specific integrated circuit (ASIC) proposed in this paper is - to the best of our knowledge - the most area-throughput efficient VLSI architecture reported so far, outperforming the second best by a factor of 1.7×. The ASIC achieves the IEEE 802.11n standard´s peak data rate of 600 Mbit/s.