A novel fully integrated low-power CMOS BPSK demodulator for medical implantable receivers

Novel low-power binary phase shift keying demodulator architectures are presented. The designs employ a phase frequency detector based phase-locked loop allowing for robust performance. Two different circuit implementations for the novel demodulator architecture are proposed. Based on the theoretical analysis, the maximum data rate of the demodulator is derived to be 1/5th of the carrier frequency. For experimental validation, a prototype was implemented for a 4MHz down-converted signal in a low-IF digital receiver. The circuit occupies 240um² chip area in a 0.13μm CMOS technology and consumes 0.324mW power with circuit optimization. The bit-error rate is measured to estimate the performance of the demodulator.