A single-ended disturb-free 5T loadless SRAM with leakage sensor and read delay compensation using 40 nm CMOS process

Author

Chua-Chin Wang ; Chiang-Hsiang Liao ; Sih-Yu Chen

Author_Institution

Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan

fYear

2014

fDate

1-5 June 2014

Firstpage

1126

Lastpage

1129

Abstract

In this study, a 4+1 Kb static random-access memory (SRAM) with leakage sensor and read delay compensation is demonstrated, where single-ended 5T loadless SRAM cells are used. The energy per access is found to be 0.27 pJ provided that the SRAM fabricated by a typical 40 nm CMOS technology is powered by a 0.6 V supply. The leakage sensor and compensation circuits are carried out by dummy SRAM cells to mimic the leakage currents therein. The average power and read delay reduction of the proposed SRAM are 27.86% and 29.46%, respectively, based on all-PT-corner post-layout simulations.

Keywords

CMOS memory circuits; SRAM chips; leakage currents; CMOS process; average power; complementary metal-oxide-semiconductor process; dummy SRAM cell; energy 0.27 pJ; leakage current; leakage sensor; read delay compensation circuit; read delay reduction; single-ended disturb-free 5T loadless SRAM; size 40 nm; static random-access memory; voltage 0.6 V; CMOS integrated circuits; Delays; Integrated circuit modeling; Leakage currents; Power dissipation; SRAM cells; SRAM; compensation circuit; disturb-free; leakage sensor; single-ended;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2014 IEEE International Symposium on

Conference_Location

Melbourne VIC

Print_ISBN

978-1-4799-3431-7

Type

conf

DOI

10.1109/ISCAS.2014.6865338

Filename

6865338