Title :
A fast-locking all-digital phase locked loop in 90nm CMOS for Gigascale systems
Author :
Yi-Wei Chen ; Hao-Chiao Hong
Author_Institution :
Dept. of Electr. & Comput. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
This paper presents an all-digital phase locked loop (ADPLL) design that features fast frequency locking and a wide tuning range. The all-digital implementation makes the design well suit Gigascale systems in advanced technology. The proposed ADPLL first uses the Regula Falsi method to fast lock the output frequency. Then, a frequency tracking (FT) loop is enabled to stabilize the output frequency against environmental disturbance as conventional PLL does. A test chip has been fabricated in 90 nm CMOS. Measurement results show the proposed ADPLL locks in 7 cycles and provides output frequencies ranging from 460.1 MHz to 6.117 GHz.
Keywords :
CMOS digital integrated circuits; UHF integrated circuits; digital phase locked loops; microwave integrated circuits; ADPLL design; CMOS; FT loop; Gigascale systems; environmental disturbance; fast frequency locking; fast-locking all-digital phase locked loop; frequency 460.1 MHz to 6.117 GHz; frequency tracking loop; output frequency stabilization; regula falsi method; size 90 nm; test chip fabrication; wide tuning range; Frequency locked loops; Frequency measurement; Jitter; Phase locked loops; Radiation detectors; Tracking loops; Tuning;
Conference_Titel :
Circuits and Systems (ISCAS), 2014 IEEE International Symposium on
Conference_Location :
Melbourne VIC
Print_ISBN :
978-1-4799-3431-7
DOI :
10.1109/ISCAS.2014.6865340
