A unique and robust single slice FPGA identification generator

Author

Chongyan Gu ; Murphy, John ; O´Neill, Maire

Author_Institution

Sch. of EEECS, Queen´s Univ. Belfast, Belfast, UK

fYear

2014

fDate

1-5 June 2014

Firstpage

1223

Lastpage

1226

Abstract

In this paper, a new field-programmable gate array (FPGA) identification generator circuit is introduced based on physically unclonable function (PUF) technology. The new identification generator is able to convert flip-flop delay path variations to unique n-bit digital identifiers (IDs), while requiring only a single slice per ID bit by using 1-bit ID cells formed as hard-macros. An exemplary 128-bit identification generator is implemented on ten Xilinx Spartan-6 FPGA devices. Experimental results show an uniqueness of 48.52%, and reliability of 92.41% over a 25°C to 70°C temperature range and 10% fluctuation in supply voltage.

Keywords

field programmable gate arrays; flip-flops; PUF technology; Xilinx Spartan-6 FPGA devices; field-programmable gate array; flip-flop delay path variation; hard-macros; physically unclonable function technology; robust single-slice FPGA identification generator; temperature 25 degC to 70 degC; unique n-bit digital identifiers; word length 1 bit; word length 128 bit; Arrays; Delays; Field programmable gate arrays; Generators; Integrated circuit reliability; Routing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2014 IEEE International Symposium on

Conference_Location

Melbourne VIC

Print_ISBN

978-1-4799-3431-7

Type

conf

DOI

10.1109/ISCAS.2014.6865362

Filename

6865362