High-speed multiplier block design based on bit-level critical path optimization

Multiple constant multiplications (MCM) is a popular technique to implement multiplier blocks with low hardware cost and power consumption. Research works on MCM have been on going for more than two decades. Most algorithms so far have focused on reducing the number of adders and/or adder depth to have low power and/or high speed circuit. However, low adder depth does not guarantee the low critical path examined in bit-level. In this work, we propose an algorithm to optimize the critical path of multiplier blocks in bit-level. Simulation results show that the critical path delay can be reduced by using the proposed algorithm.