Title :
A 1-GS/s 11.5-ENOB time-interleaved ADC with fully digital background calibration
Author :
Nakamura, Yoshihiko ; Oshima, Toru
Author_Institution :
Central Res. Lab., Hitachi, Ltd., Tokyo, Japan
Abstract :
A 1-GS/s 11.5-ENOB (71.2-dB-SNDR) time-interleaved analog-to-digital converter with fully digital background calibration was demonstrated. To generate multi-phased sampling clocks with low noise and low power, passive delay circuits with a differential-clock-sharing structure are proposed. A double filter for reducing sub-ADC kickback combined with bandwidth-mismatch calibration is also proposed. The proposed techniques are essential to assure accurate sampling. This is considered to be the first giga-sampling-rate ADC with over-70-dB SNDR and over-80-dB SFDR.
Keywords :
analogue-digital conversion; calibration; delay circuits; passive networks; signal processing equipment; ENOB; SFDR; SNDR; analog-to-digital converter; bandwidth-mismatch calibration; differential-clock-sharing structure; double filter; effective number of bits; fully digital background calibration; giga-sampling-rate ADC; multiphased sampling clock; passive delay circuit; signal-to-noise distortion ratio; spurious-free dynamic range; subADC kickback reduction; time-interleaved ADC; Bandwidth; Calibration; Clocks; Delays; Finite impulse response filters; bandwidth mismatch; digital calibration; kickback; time-interleaved ADC;
Conference_Titel :
Circuits and Systems (ISCAS), 2014 IEEE International Symposium on
Conference_Location :
Melbourne VIC
Print_ISBN :
978-1-4799-3431-7
DOI :
10.1109/ISCAS.2014.6865389
