Title :
A low power 4th order MASH switched-capacitor ΣΔ modulator using ultra incomplete settling
Author :
Nowacki, Blazej ; Paulino, Nuno ; Goes, Johannes
Author_Institution :
Dept. de Eng. Electrotec., Univ. Nova de Lisboa, Lisbon, Portugal
Abstract :
A discrete-time, switched-capacitor, MASH 2-2 4th order ΣΔ modulator, clocked with frequency of 1 GHz, was designed in a 65 nm CMOS technology. This modulator uses passive integrators based on the ultra-incomplete settling (UIS) concept. Electrical simulations show that the modulator achieves a peak SNDR of 66.8 dB, a peak SNR of 67.7 dB, an ENOB of 10.8 bits and DR of 70dB for a signal with a bandwidth of 10 MHz, while dissipating 1.5 mW from a 1.1 V power supply voltage, indicating that, a FOM of 42.7 fJ/conv.-step can be reached.
Keywords :
CMOS integrated circuits; low-power electronics; modulators; sigma-delta modulation; switched capacitor networks; CMOS technology; discrete-time; electrical simulations; frequency 1 GHz; frequency 10 MHz; low power 4th order MASH switched-capacitor ΣΔ modulator; passive integrators; power 1.5 mW; power supply voltage; size 65 nm; ultra-incomplete settling concept; voltage 1.1 V; word length 10.8 bit; Capacitors; Clocks; Gain; Modulation; Multi-stage noise shaping; Noise; Quantization (signal); Cascaded delta-sigma modulator; MASH; analog-to-digital (A/D) conversion; passive SC filter; passive integrator;
Conference_Titel :
Circuits and Systems (ISCAS), 2014 IEEE International Symposium on
Conference_Location :
Melbourne VIC
Print_ISBN :
978-1-4799-3431-7
DOI :
10.1109/ISCAS.2014.6865392
