A low power 4th order MASH switched-capacitor ΣΔ modulator using ultra incomplete settling

A discrete-time, switched-capacitor, MASH 2-2 4^th order ΣΔ modulator, clocked with frequency of 1 GHz, was designed in a 65 nm CMOS technology. This modulator uses passive integrators based on the ultra-incomplete settling (UIS) concept. Electrical simulations show that the modulator achieves a peak SNDR of 66.8 dB, a peak SNR of 67.7 dB, an ENOB of 10.8 bits and DR of 70dB for a signal with a bandwidth of 10 MHz, while dissipating 1.5 mW from a 1.1 V power supply voltage, indicating that, a FOM of 42.7 fJ/conv.-step can be reached.