State dependent statistical timing model for voltage scaled circuits

Author

Pirbadian, Aras ; Khairy, Muhammad S. ; Eltawil, Ahmed M. ; Kurdahi, F.J.

Author_Institution

Electr. Eng. & Comput. Sci. Dept., Univ. of California, Irvine, Irvine, CA, USA

fYear

2014

fDate

1-5 June 2014

Firstpage

1432

Lastpage

1435

Abstract

This paper presents a novel statistical state-dependent timing model for voltage over scaled (VoS) logic circuits that accurately and rapidly finds the timing distribution of output bits. Using this model erroneous VoS circuits can be represented as error-free circuits combined with an error-injector. A case study of a two point DFT unit employing the proposed model is presented and compared to HSPICE circuit simulation. Results show an accurate match, with significant speedup gains.

Keywords

CMOS logic circuits; integrated circuit modelling; integrated circuit reliability; logic design; logic testing; statistical analysis; timing; error free circuits; error injector; state dependent statistical timing model; timing distribution; two point DFT; voltage over scaled logic circuits; voltage scaled circuit; Discrete Fourier transforms; Integrated circuit modeling; Logic circuits; Logic gates; Mathematical model; Monte Carlo methods; Timing; propagation delay; timing model; voltage scaling;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2014 IEEE International Symposium on

Conference_Location

Melbourne VIC

Print_ISBN

978-1-4799-3431-7

Type

conf

DOI

10.1109/ISCAS.2014.6865414

Filename

6865414