Title :
A 20-Gb/s 1.27pJ/b low-power optical receiver front-end in 65nm CMOS
Author :
Gyu-Seob Jeong ; Hankyu Chi ; Kyungock Kim ; Deog-Kyoon Jeong
Author_Institution :
Dept. of Electr. Eng., Seoul Nat. Univ., Seoul, South Korea
Abstract :
This paper describes a CMOS interface circuit for silicon photonics. 20-Gb/s operation of an optical receiver front-end circuit is demonstrated using an optical signal applied to the optical front-end. The transimpedance amplifier (TIA) is based on an inverter with resistive and inductive feedback for low power consumption and frequency compensation. A negative capacitance generation is employed in the limiting amplifier (LA) for bandwidth extension. The combined TIA and LA block exhibits a transimpedance gain of 78 dBΩ and a bandwidth of 11 GHz. The TIA and the LA block consume 1.3 mA and 24 mA at 1 V supply voltage, respectively.
Keywords :
CMOS integrated circuits; circuit feedback; integrated optoelectronics; low-power electronics; operational amplifiers; optical receivers; CMOS interface circuit; CMOS process; LA block; TIA block; bandwidth 11 GHz; bandwidth extension; bit rate 20 Gbit/s; current 1.3 mA; current 24 mA; frequency compensation; inductive feedback; inverter; limiting amplifier; low power consumption; low-power optical receiver front-end circuit; negative capacitance generation; optical signal; resistive feedback; silicon photonics; size 65 nm; transimpedance amplifier; voltage 1 V; Bandwidth; CMOS integrated circuits; Noise; Optical fibers; Optical receivers; Semiconductor device measurement; CMOS; limiting amplifier (LA); optical receiver front-end; silicon photonics; transimpedance amplifier (TIA);
Conference_Titel :
Circuits and Systems (ISCAS), 2014 IEEE International Symposium on
Conference_Location :
Melbourne VIC
Print_ISBN :
978-1-4799-3431-7
DOI :
10.1109/ISCAS.2014.6865429
