A variation tolerant driving technique for all-digital self-timed 3-level signaling high-speed SerDes transceivers for on-chip networks

This paper presents a variation tolerant driving technique for all-digital self-timed 3-level signaling high-speed SerDes transceivers. The proposed design generates the 3-level signal without a ½VDD driver, thus removing all the overhead and hassle of an additional supply. Moreover, the proposed all-digital scheme uses half the clock frequency while maintaining the same data rate of the conventional scheme. As a result, the proposed design is much more robust across all possible variations. The transceiver is designed for a 3mm long lossy on-chip differential interconnect in TSMC 65nm CMOS technology. The transmitter serializes the parallel 1.9375Gbps 8-bit, then multiplexes it with the 15.5GHz clock to generate the three level signal on the differential TL, and a simple RX detects both the data and the clock from the signal.