DocumentCode
1768925
Title
Area-efficient and fast sign detection for four-moduli set RNS {2n −1,2n, 2n +1,22n +1}
Author
Chip-Hong Chang ; Kumar, Sudhakar
Author_Institution
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore
fYear
2014
fDate
1-5 June 2014
Firstpage
1540
Lastpage
1543
Abstract
Sign detection is a necessary but non-trivial operation in Residue Number System (RNS) for many digital signal processing applications. Efficient sign detector for the three-moduli set RNS {2n -1,2n, 2n +1} has been proposed, but the problem remains unsolved for its extended four moduli sets. This paper presents a new sign detection algorithm dedicated to {2n -1,2n, 2n +1,22n +1} RNS that has a wider dynamic range and higher parallelism. Our approach exploits the number theoretic and multiplicative inverse properties in two-residue Chinese Remainder Theorem (CRT) and the New CRT II to halve the bit width of the modulo additions required by a complete reverse conversion. Our synthesis results show greater than 60% area reduction and more than 40% speedup for n = 2 to 5 compared with using its most efficient reverse converter for sign detection.
Keywords
discrete Fourier transforms; set theory; signal processing; wavelet transforms; CRT; Chinese remainder theorem; area efficient detection; digital signal processing applications; fast sign detection; four moduli set RNS; moduli sets; residue number system; reverse converter; sign detection algorithm; Adders; Computer architecture; Delays; Detectors; Dynamic range; Hardware; Logic gates;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), 2014 IEEE International Symposium on
Conference_Location
Melbourne VIC
Print_ISBN
978-1-4799-3431-7
Type
conf
DOI
10.1109/ISCAS.2014.6865441
Filename
6865441
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