Design of a 5 GS/s fully-digital digital-to-analog converter

We present a fully-digital digital-to-analog converter (FD DAC) architecture design for high-speed communication systems. The FD DAC design is based on the ΔΣ modulation. The specifications for the DAC includes a low 1.2 V supply voltage, a high 5 GS/s input sampling rate, and a wide 2.5 GHz bandwidth. We employ a combination of the time-interleaving, parallel, and pipelining techniques to reduce the clock speed from 10 GHz to 625 MHz. The lower clock speed allows the use of standard cells for designing the digital computational circuits of the FD DAC. The critical building blocks of the FD DAC are laid-out in a 65 nm CMOS process. The post-layout simulation results show that the Signal to Noise and Distortion Ratio and the in-band Spurious-Free Dynamic Range of the output signal are 36 dB and 44 dBc respectively.