A generalised conductance-based silicon neuron for large-scale spiking neural networks

We present an analogue Very Large Scale Integration (aVLSI) implementation that uses first-order log-domain low-pass filters to implement a generalised conductance-based silicon neuron. It consists of a single synapse, which is capable of linearly summing both the excitatory and inhibitory post-synaptic currents (EPSC and IPSC) generated by the spikes arriving from different sources, a soma with a positive feedback circuit, a refractory period and spike-frequency adaptation circuit, and a high-speed synchronous Address Event Representation (AER) handshaking circuit. To increase programmability, the inputs to the neuron are digital spikes, the durations of which are modulated according to their weights. The proposed neuron is a compact design (~170 μm² in the IBM 130nm process). Our aVLSI generalised conductance-based neuron is therefore practical for large-scale reconfigurable spiking neural networks running in real time. Circuit simulations show that this neuron can emulate different spiking behaviours observed in biological neurons.