CheckerBoard binary CNN core

The 3D integration of Cellular Nonlinear Network architectures offers possibilities to increase the pixel and processor count remarkably by allowing integration of different processor functionalities to different chip layers. On the other hand, to avoid extensive use of Through Silicon Vias for inter and intracellular communication, it is important to be able to fit to each layer of silicon as complete parts of processor structures as possible. In this article we propose a CheckerBoard CNN architecture for binary image processing that is able to reduce the required hardware while simultaneously preserving the full functionality. Although rather simple examples are given, the design ideology can be considered to be extended to other functionalities as well. Simulation results of propagation intensive binary template Holefiller are given.