Design of a wideband low power FMCW synthesizer in 65 nm CMOS for radar applications

The paper presents a design of a low power wide output bandwidth FMCW frequency synthesizer for radar applications. The proposed FMCW frequency synthesizer adopts digital phase locked loop approach and has been implemented in 65 nm CMOS technology. A phase domain model is proposed for analyzing the digital phase locked loop architecture. The FMCW synthesizer is able to generate triangularly modulated continuous wave of 3GHz output bandwidth in X band with linearity error less than 1.4×10^-4. It consumes only 7 mA under 1.2 V power supply. The measured phase noise is -105dBc/Hz at 1MHz offset with a centre frequency of 10 GHz.