Energy-aware current-mode inter-chip link for a dependable GALS NoC platform

Author

Shirahama, Hirokatsu ; Mochizuki, Akira ; Watanabe, Yoshihiro ; Hanyu, Takahiro

Author_Institution

Res. Inst. of Electr. Commun., Tohoku Univ., Sendai, Japan

fYear

2014

fDate

1-5 June 2014

Firstpage

1865

Lastpage

1868

Abstract

An inter-chip communication link with high-speed and low-energy capabilities is proposed for a dependable globally-asynchronous-locally-synchronous (GALS) network-on-chip (NoC) platform. The use of a dynamic current feedback mechanism in the link makes a current driving capability high and a signal voltage swing small, which accelerates the switching speed. The power-gating technique is also applied to greatly reduce the power dissipation since the inter-chip communication links are supposed to have long idle time in the dependable GALS NoC platform. It is demonstrated that the proposed circuit with a 1cm transmission line achieves the transmission rate of 2.8Gbps while consuming 1.1uW in a 130nm CMOS technology at the power supply of 1.2V.

Keywords

CMOS digital integrated circuits; circuit feedback; network-on-chip; CMOS technology; bit rate 2.8 Gbit/s; dependable GALS NoC platform; driving capability; dynamic current feedback mechanism; energy-aware current-mode interchip link; globally-asynchronous-locally-synchronous platform; high-speed capabilities; interchip communication link; low-energy capabilities; network-on-chip platform; power 1.1 muW; power-gating technique; signal voltage swing; size 130 nm; switching speed; voltage 1.2 V; CMOS integrated circuits; Data communication; Detectors; Discharges (electric); Power dissipation; Power transmission lines; System-on-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2014 IEEE International Symposium on

Conference_Location

Melbourne VIC

Print_ISBN

978-1-4799-3431-7

Type

conf

DOI

10.1109/ISCAS.2014.6865522

Filename

6865522