A 10-Gb/s 6-Vpp differential modulator driver in 65-nm CMOS

Author

Yoonsoo Kim ; Woorham Bae ; Deog-Kyoon Jeong

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul, South Korea

fYear

2014

fDate

1-5 June 2014

Firstpage

1869

Lastpage

1872

Abstract

A 10-Gb/s 6-V_pp differential Mach-Zehnder modulator driver is implemented in 65-nm CMOS technology. The proposed modulator driver adopts a triple-stacking topology with a dynamic biasing to generate the differential voltage swing of six times as much as the nominal supply. The modulator driver occupies only 0.04 mm² without using inductors for area efficiency. The measurement results show an operating speed up to 10 Gb/s when electrically measured. The power consumption of this modulator driver is 98 mW which is lower than that of other modulator drivers exhibiting more than 6-V_pp swing.

Keywords

CMOS analogue integrated circuits; driver circuits; modulators; optical modulation; CMOS technology; area efficiency; bit rate 10 Gbit/s; differential Mach-Zehnder modulator driver; differential voltage swing; dynamic biasing; inductors; nominal supply; power 98 mW; power consumption; size 65 nm; triple-stacking topology; voltage 6 V; CMOS integrated circuits; Logic gates; Modulation; Semiconductor device measurement; Steady-state; Stress; Transistors; fiber-optic communication; modulator driver;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2014 IEEE International Symposium on

Conference_Location

Melbourne VIC

Print_ISBN

978-1-4799-3431-7

Type

conf

DOI

10.1109/ISCAS.2014.6865523

Filename

6865523