A 100 Gb/s transimpedance amplifier in 65 nm CMOS technology for optical communications

A 100 Gb/s CMOS transimpedance amplifier (TIA) for high speed optical communication receivers is presented in this paper. The TIA is based on a differential architecture and composed of a regulated cascode block and a differential amplifier with active feedback. It adopts peaking inductors and a capacitive degeneration scheme to increase the bandwidth. The TIA is designed and laid out in CMOS 65 nm CMOS technology. Post layout simulation results show that the TIA achieves 70 GHz bandwidth, 40 dBO transimpedance gain, ±4.36 ps of the group delay variation, and 31 pA/√Hz of the input referred noise current, and it dissipates 24 mW under 1.2V supply. The proposed TIA increases the bandwidth by more than two times when compared with other existing CMOS TIAs, while achieving comparable performance in other performance metrics.