High-voltage tolerant circuit design for fully CMOS compatible multiple-time programmable memories

Author

ChihYang Huang ; Hongchin Lin ; Chia-You Wu

Author_Institution

Dept. of Electr. Eng., Nat. Chung Hsing Univ., Taichung, Taiwan

fYear

2014

fDate

1-5 June 2014

Firstpage

1949

Lastpage

1952

Abstract

A fully CMOS compatible embedded multiple-time programmable (MTP) memory system using the standard TSMC 0.35 μm CMOS process is presented. The memory cells and the control circuits without extra processing steps do not violate design/electrical rules. By employing the high-voltage tolerant circuit design techniques with the current sense amplifiers, the simulation and measurement results reveal the random access time reaches 11 ns and 13 ns, respectively, after program. It is a cost-effective solution to have CMOS compatible embedded non-volatile memory systems for systems-on-chip (SOC) applications.

Keywords

CMOS memory circuits; integrated circuit design; power amplifiers; power integrated circuits; programmable circuits; random-access storage; system-on-chip; CMOS compatible embedded nonvolatile memory system; MTP memory system; SOC application; current sense amplifier; fully CMOS compatible multiple-time programmable memory; high-voltage tolerant circuit design technique; size 0.35 mum; standard TSMC CMOS process; systems-on-chip application; time 11 ns; time 13 ns; Arrays; CMOS integrated circuits; CMOS process; MOSFET; Nonvolatile memory; Random access memory; Sensors;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2014 IEEE International Symposium on

Conference_Location

Melbourne VIC

Print_ISBN

978-1-4799-3431-7

Type

conf

DOI

10.1109/ISCAS.2014.6865543

Filename

6865543