DocumentCode :
1769118
Title :
A signal processor for Gaussian message passing
Author :
Kroll, Harald ; Zwicky, Stefan ; Odermatt, Reto ; Bruderer, Lukas ; Burg, Andreas ; Qiuting Huang
Author_Institution :
Integrated Syst. Lab., ETH Zurich, Zurich, Switzerland
fYear :
2014
fDate :
1-5 June 2014
Firstpage :
1969
Lastpage :
1972
Abstract :
In this paper, we present a novel signal processing unit built upon the theory of factor graphs, which is able to address a wide range of signal processing algorithms. More specifically, the demonstrated factor graph processor (FGP) is tailored to Gaussian message passing algorithms. We show how to use a highly configurable systolic array to solve the message update equations of nodes in a factor graph efficiently. A proper instruction set and compilation procedure is presented. In a recursive least squares channel estimation example we show that the FGP can compute a message update faster than a state-of-the-art DSP. The results demonstrate the usabilty of the FGP architecture as a flexible HW accelerator for signal-processing and communication systems.
Keywords :
Gaussian processes; application specific integrated circuits; channel estimation; digital signal processing chips; graph theory; instruction sets; least squares approximations; message passing; recursive functions; systolic arrays; ASIP; FGP; Gaussian message passing; application specific instruction set processor; factor graph processor; instruction set; recursive least squares channel estimation; signal processing unit; systolic array; Arrays; Channel estimation; Compounds; Digital signal processing; Signal processing algorithms; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2014 IEEE International Symposium on
Conference_Location :
Melbourne VIC
Print_ISBN :
978-1-4799-3431-7
Type :
conf
DOI :
10.1109/ISCAS.2014.6865548
Filename :
6865548
Link To Document :
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