DocumentCode
1769188
Title
A simple digital architecture for a harmonic-cancelling sine-wave synthesizer
Author
Aluthwala, Pasindu ; Weste, Neil ; Adams, Andrew ; Lehmann, T. ; Parameswaran, Sri
Author_Institution
Univ. of New South Wales, Sydney, NSW, Australia
fYear
2014
fDate
1-5 June 2014
Firstpage
2113
Lastpage
2116
Abstract
Sine-wave synthesizers are a core requirement in many electronic applications, such as communication systems, and test and verification of analog/mixed-signal electronic systems. In sine-wave synthesizers, there exists a compromise between output spectral purity and hardware complexity. Harmonic-cancelling sine-wave synthesizers (HCSSs) allow spectrally pure signal synthesis at low hardware cost, compared to conventional sine-wave synthesis approaches. In this paper, we propose a digital HCSS hardware architecture, which is simpler, more hardware efficient and more programmable compared to state of the art HCSSs. The proposed architecture has been verified through a prototype built from an FPGA and discrete components. Prototype results demonstrate 51.9 dBc spurious free dynamic range (SFDR) and an output frequency range from 100 Hz to 100 kHz.
Keywords
direct digital synthesis; harmonics suppression; signal synthesis; FPGA; SFDR; analog-mixed-signal electronic systems; communication systems; digital HCSS hardware architecture; digital architecture; discrete components; frequency 100 Hz to 100 kHz; hardware complexity; harmonic-cancelling sine-wave synthesizer; low hardware cost; output spectral purity; signal synthesis; spurious free dynamic range; Clocks; Digital circuits; Hardware; Harmonic analysis; Power harmonic filters; Prototypes; Synthesizers; Sinusoids; digital-oscillator; low harmonic distortion;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), 2014 IEEE International Symposium on
Conference_Location
Melbourne VIC
Print_ISBN
978-1-4799-3431-7
Type
conf
DOI
10.1109/ISCAS.2014.6865584
Filename
6865584
Link To Document