An area- and power-efficient half-rate clock and data recovery circuit

This paper presents a 3.2 Gb/s low-power clock and data recovery (CDR). The improved architecture using two half-rate gated voltage-controlled oscillators (GVCOs) shared between frequency presetting and data recovery modes is presented to remove the LC-tank voltage-controlled oscillator in a cascaded CDR. Moreover, using the proposed active inductive loading technique instead of the on-chip inductor reduces the power consumption and area in high-speed operation. This CDR circuit has been designed in TSMC 0.18 μm CMOS technology. It consumes 22.5 mW from a 1.8-V supply and occupies an active area of 0.26 mm². The peak-to-peak and rms jitter of the recovered clock are 95.6 ps and 12.1 ps for a 3.2 Gb/s 2⁷-1 PRBS, respectively.