Design of low-leakage multi-port SRAM for register file in graphics processing unit

This paper combines several low-leakage and low-cost techniques to design multi-port static random access memory (SRAM) for register file in a vertex shader processor for OpenGL ES 2.0 graphics applications. First, precharge control is employed to eliminate unnecessary precharge operations. Then, dynamic forward body-bias control for leakage reduction is proposed to adjust the threshold voltage of transistors depending on whether memory cell is accessed or idle. Different power-gating methods are presented for SRAM cells and for sense amplifiers. The thin-cell-like lithography-friendly layout style is adopted for the multi-port SRAM cell to achieve more compact and flexible layout with easy addition of read ports. The cross-coupled inverters in the SRAM cell have asymmetric design to reduce area and also increase the writability. A 32×128-bit register file supporting 5-read and 1-write operations is implemented and verified, which has smaller area and lower leakage compared with that from ARM register file generator.